Unit 02 Arithmetic and Logic Unit in Computer Organization and Architecture

The Arithmetic and Logic Unit (ALU) is covered in Unit 02 of Computer Organization and Architecture. It is the CPU’s core component that performs arithmetic and logic tasks. This unit covers Boolean algebra, half and full adders, binary adders, subtractors, comparators, and multipliers.

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Important Questions For Computer Organization and Architecture:
*Unit-01     *Unit-02    
*Unit-03    *Unit-04 
*Unit-05    *Short-Q/Ans
*Question-Paper with solution 21-22 

Q1. Describe sequential Arithmetic and Logic Unit (ALU) using proper diagram. 

Ans.

• 1. With the aid of a multiplexer, we may combine arithmetic and logic circuits to create arithmetic and logic units.

• 2. When the mode select line S₂ =0, this ALU acts as an arithmetic circuit so the output of arithmetic circuit is transferred as final output. 
• 3. Otherwise (S₂ = 1) the output of the logic circuit is transferred as final output. 
• 4. Based on the mode select S₂ and input carry C_in. we increase or decrease the number of arithmetic and logic operations.
• 5. When S₂ = 0, the ALU performs arithmetic operation and when S₂ =1, with C_in = 0, the ALU performs logic operations. 
• 6. We know that the carry input is not required in the logie circuits. 
• 7. When logic operation is selected (S₂ = 1), the carry input must be zero. 
• 8. This given us the output sum in full adder circuit as

Q2. Explain Booth’s multiplication algorithm in detail.

Ans. The algorithm for 2’s complement multiplication is as follows:

Step 1: Load multiplicand in B, multiplier in Q. For negative numbers, 2’s complement format to be used. 

Step 2 : Initialize the down counter CR by the number of bits involved. 

Q3. Give the Robertson multiplication algorithm for 2’s compliment fractions. Also illustrate the algorithm for 2’s compliment fraction by a suitable example.

Ans. Robertson algorithm: 

1. A ← 0,B ← Multiplicand Q ← Multiplier and count ←n. 

2. If Q_o = 1 then perform A ← A+ B. 

3.Shift right register F.A.Q by 1 bit F ← B [n – 1] AND Q [0] OR F and count ← count- 1. 

4. If count > 1 Repeat steps 2 and 3, otherwise if Q_o = 1 then perform A ← A-B and set Q [0] = 0. 

For example: We perform the multiplication of fraction as: 

Multiplicand = 0.625 

Multiplier = 0.5 

Equivalent binary representation 0.625 = 0101 

2’s complement representation-0.625 = 1010 + 1(-0.625) = 1011 

Equivalent binary representation +0.5 = 0100 

2 complement representation – 0.5 = 1011 + 1-0.5 = 1100  

Q4. Show step by step the multiplication process using Booth’s algorithm when (+ 15) and (- 13) numbers are multiplied. Assume 5-bit registers that hold signed numbers. 

Ans. 15 01111 

– 13 = 2’s complement of 13 = 10011 

Multiplicand (M) = 01111, Multiplier = 10011 

Q5. Show the contents of the registers E, A, Q, SC during the process of multiplication of two binary numbers 11111 (multiplicand) 10101 (multiplier). The signs are not included.

Ans. 

Q6. Show the multiplication process using Booth’s algorithm when the following numbers are multiplied: (-13) by (+8) 

Ans. 

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