# Important Short Question in Computer Organization and Architecture

If you are studying Computer Organization and Architecture as part of your AKTU B.Tech. degree, you should practice short questions to improve your comprehension. These brief questions cover a wide range of ideas and subjects, including the fundamentals of computer architecture, CPU components, memory hierarchy, I/O devices, and more. Regularly practicing these questions will help you enhance your problem-solving abilities and prepare you for tests. Make sure to go through your course materials and lectures again to ensure you have a thorough comprehension of the subject.

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Important Questions For Computer Organization and Architecture:
*Unit-01     *Unit-02
*Unit-03    *Unit-04
*Unit-05    *Short-Q/Ans
*Question-Paper with solution 21-22 ```

## Unit – 1 Introduction | Important Notes

Q1. What are the various ways of specifying the binary point in a register ?

Ans. There are two ways of specifying the binary point in a register which aré :

• i. By giving it a fixed position.
• ii. By employing a floating-point representation.

Q2. What are the various facts related to bus and bus system ?

Ans. Various facts related to bus and bus system are :

• i. In a bus system, k registers with n bits each are multiplexed to create an n-line common bus.
• ii. The amount of bits in each register, n, determines how many multiplexers are required to build the bus.
• iii. The size of each multiplexer must be k x 1, since it multiplexes / data lines.

Q3.  Give various advantages of polling method.

Ans. Various advantages of polling method are :

• i. By changing the polling sequence that is stored in the controller, the priority can be modified.
• ii. If the one module fails, entire system does not fail.

Q4. Discuss the basic component of register transfer logic.

Ans. Basic components of register transfer logic are:

• i. Registers and their functions
• ii. Information
• iii. Operations
• iv. Control function

Q5. What is the relation between bus width and number of bit transferred ?

Ans. The number of bits conveyed is directly proportional to bus width. The amount of bits that can be transferred at once will increase as the data bus becomes bigger.

Q6. Define memory transfer.

Ans. Basic operations like fetch (read) and store are a part of memory transfer (write). An exact copy of the content is sent from memory to the CPU during the fetch procedure. The store process moves word data from the CPU to a specific location in memory.

Q7. Define bus transfer.

Ans. Bus transfer is the term used to describe the data exchange between different blocks connected to a common bus. All of the units share a same bus system.

Q8.  Explain control word.

Ans. A control word is a word whose constituent bits stand in for the different control signals. As a result, every control step in an instruction’s control sequence defines a different set of 0s and 1s.

Q9. Compare register stack and memory stack.

Ans.

## Unit – 2 Arithmetic and Logic Unit | AKTU Btech Important Shorts

Ans. A look forward A form of adder called a carry adder increases speed by cutting down on the time needed to determine the carry bits.

Q2. What is arithmetic and logic circuit ?

Ans. Arithmetic circuit : In a digital circuit called t, only arithmetic operations like addition, subtraction, etc. are performed.

Logic circuit : This digital circuit exclusively does logical operations like AND, OR, and NOT, etc.

Q3. Define following terms:

i. RTL                                        ii. Micro-operation

Ans. i. RTL : The Register Transfer Language (RTL) is a useful tool for succinctly and precisely defining the underlying structure of digital computers. Additionally, it can be applied to simplify the creation of digital system designs.

ii Micro-operation : The key steps of the instruction cycle need the processor unit to carry out a set of tasks known as micro-operations.

Q4. What is the main advantage of RTL ?

• i. As a basic element of the digital system, registers are used rather than flip-flops and gates.
• ii. It succinctly and precisely specifies the information flow and processing tasks among the data contained in the registers.
• iii. It employs a number of statements and phrases that are similar to the I statements used in programming languages. iv. In register transfer logie, the presentation of digital functions is particularly user-friendly.

Q5. What is the need of having many addressing modes in machine ?

Ans. Need of having many addressing modes in machine is due to following reason: i. The addressing mode of the instruction determines how operands are selected during programme execution.

ii. Before the operand is actually referenced in the instruction, the addressing mode sets a rule for interpreting or changing the address field.

Q6. How subtraction operation and other operations can be simplified in a digital system?

Ans. The complement method can be used in a digital system to simplify operations such as subtraction and other operations. For each number system, there are two types of complement:

i. r’s complement                          ii. (r-1)’s complement

Q7. How many flip-flops are needed for 4-bit decimal code and 4385 in BCD representations?

Ans. Four flip-flops, one for each bit of a 4-bit decimal code, are employed. There are 16 flip-flops used to represent the number 4385 in BCD format.

Q8. State the condition for floating-point number to become normalized.

Ans. If a floating-point number’s mantissa’s most significant digit is not zero, the value is said to be normalized.

Q9. When exponent overflow and underflow occur ?

Ans. When a positive exponent surpasses the highest allowed exponent value, this is known as exponent overflow. When a negative exponent surpasses the highest allowable exponent value, exponent underflow occurs. The intended number in these circumstances is zero.

Q10. Perform the following operation on signed numbers using 2’s compliment method: (56)10+(-27)10.

Ans.

## Unit – 3 Control Unit | Quantum Notes is Available on Books Section

Q1. Explain one, two and three address instruction.

Ans. i. One address instruction : An inferred accumulator (AC) register is used for all data modification in a single address instruction.

ii. Two address instruction : Each address field in this format can be either a processor register or a memory word.

iii. Three address instruction : Each address field in the three address instruction types can be used to designate a CPU register or a memory operand.

Q2. What are the various facts related to operation code?

Ans. Various facts related to operation code are :

i. The total amount of operations a computer can perform determines how many bits are needed for an instruction’s operation code.

ii. The operation code must consist of at least n bits for a given 2n distinct operations.

Q3. Define the necessary factors for instruction sequencing.

Ans. Necessary factors for instruction sequencing are :

i. To determine the address of the following instruction after the current instruction has been executed, a counter is required.

ii. Additionally, a register in the control unit must be provided for the storage of the instruction code.

Q4. What operations are included in micro-operations?

Ans. Micro-operations íncludes:

• i. Transfer a word of data from one CPU register to another or to the ALU.
• ii. Apply logic or arithmetic operations to the information in the CPU registers, and then store the outcome in a CPU register.
• iii.Obtain a word of data from a specific address in memory, then load it into a CPU register.
• iv. Store a word of data from a CPU register into a specified memory location.

Q5. Define the following terms:

ii. Immediate instruction

Ans. i. Effective address: The target address in a branch type instruction or the address of the operand in a computation type instruction is the effective address.

ii. Immediate instruction: An operand field, as opposed to an address field, is present in an instantaneous mode instruction. The actual operand to be utilized in combination with the operation mentioned in the instruction is contained in the operand field.

Q6. What does the processor do when an interrupt is pending ?

Ans. If an interrupt is pending, the processor does the following:

i. It preserves the context of the currently running programme while pausing execution.

ii. The interrupt handler routine’s beginning address is set as the programme counter.

Q7. Define the goal of CISC architecture.

Ans. Each statement expressed in high-level language should have a single machine instruction, according to the CISC architecture.

Q8.Compare horizontal and vertical organization

Ans.

Q9. Describe the micro-program sequencing

Ans. Except for the branch at the conclusion of the fetch phase, the straightforward method of micro-programming consists of the sequential execution of micro-instructions.

Q10. What is the problem with simple micro-instruction ?

Ans. A number of branch micro-instructions are needed by the micro-program. These instructions don’t do anything meaningful in the data route. They are only required to identify the location of the subsequent micro-instruction. They reduce the computer’s functioning speed as a result.

Q11. List two important instruction set design issues

Ans. Two important instruction set design issues are:

i. Data types: the numerous forms of data that are used for activities.

ii. Registers: Number of CPU registers that can be referenced by instructions and their use.

Q12. Define sequencer.

Ans. The addresses needed to step through a control store’s micro-program are generated by a sequencer. It functions as a component of the CPU’s control unit for address ranges.

Q13. List the two techniques used for grouping the control signals.

Ans. The two techniques used for grouping the control signal are:

i Hardwired control unit

ii. Micro-programmed control unit

Q14. List three types of control signals.

Ans. Three types of control signals are

• i. ALU
• ii. Data paths
• iii. System

Q15. Draw the block diagram of micro-program sequencer

Ans.

Q16.  Write short note on pipelining process.

Ans. Pipelining is a cost-effective method of achieving temporal parallelism. This breaks the problem down into a number of steps that must be taken one at a time.

Q17. Differentiate between horizontal and vertical microprogramming.

Ans.

Q18. What are the difference between horizontal and vertical micro codes?

Ans.

## Unit – 4 (Memory) Important short Question for Exams

Q1. What are the requirements of memory ?

Ans. There are three requirements of memory which are following:

• i. It should be fast.
• ii. It should be large.
• iii. It should be inexpensive.

Q2. Differentiate between SRAM and DRAM

Ans.

Q3. What do you mean by programming of ROM ?

Ans. According to the truth table, programming ROM refers to the blowing of fuses in a cell. The PROMs can be programmed just once. The information is permanently kept once it has been programmed.

Q4. Give the difference between PROM and EEPROM.

Ans.

Q5. Why auxiliary storage is organized in records or blocks ?

Ans. Because the seek time is typically significantly longer than the transfer time, auxiliary storage is structured in records or blocks.

Q6. What is CAM?

Ans. A circuit known as a Content Addressable Memory (CAM) combines store and comparing functions into a single unit. We input the data, the CAM checks to see if it has a copy, and then returns the index of the matching row rather than providing an address and reading a word like a RAM.

Q7. Which of Ll and L2 cache is faster ?

Ans. 1. Li cache, an extremely quick and expensive memory that is typically found in processors, is used by all processors.

2. L2 cache is slower, bigger and cheaper than L1 cache.

Q8. What is cache memory used for?

Ans. 1. Data or instructions that are utilized frequently are stored in cache memory.

2. By speeding up access to memory, cache memory helps computers run faster.

3. Instructions and data that are most likely to be required for the next CPU operation are stored in a cache.

Q9.  Give the disadvantage of direct mapping.

Ans. The drawback of direct mapping is that if two or more words with addresses that have the same index but different tags are continuously visited, the hit ratio may drop significantly.

Q10.  Define access time, seek time and latency time.

Ans. Access time: The period of time between receiving an address and the start of real data transmission is known as the disc access time.

Seek time: The time needed to shift the read-write head to the appropriate track is known as the seek time.

Latency time: The time that transpires between the starting position of the addressed section passing under the read/write head and the head being positioned over the right track is known as the rotational delay or latency time.

Q11. Discuss the advantages of erasable optical disk.

Ans. Advantages of erasable optical disk are:

i. Offer a 5.25-inch disc with a high storage capacity of 650 Mbytes of data.

ii. It is portable and can easily be carried from one computer to another.

iii. It is highly reliable and has longer life.

Q12. State the disadvantages of erasable optical disk.

Ans. Disadvantages of erasable optical disk are:

i. It employs the constant angular velocity approach, which wastes a significant amount of storage capacity in the outer tracks.

ii. Since erasing a bit and writing it back in requires two revolutions of the disc, overwriting data on magneto-optic media takes longer than on magnetic media.

Q13. What is memory management unit ?

Ans. The hardware element in the computer that manages virtual memory is called the Memory Management Unit (MMU). Any request for data is routed to the MMU, which then assesses whether the data is on a permanent storage disc or in RAM. A table for converting physical memory addresses to virtual ones is kept by the MMU, which is often found on the CPU of our machine.

Q14. Explain the following terms:

i. PSW

Ans. i. PSW (Program Status Word):

1. A programme status word, or PSW, is the collective name for all status bit situations in the CPU.

2. The status data that describes the condition of the CPU is contained in the PSW, which is kept in a separate hardware register.

3. In addition to detailing the permitted interrupts and indicating whether the CPU is in supervisor or user mode, it also contains the status bits from the most recent ALU operation.

1. The compiler is responsible for ensuring that the instruction that comes after the load instruction uses the information retrieved from memory.

2. A no-op (no-operation) instruction is inserted if the compiler is unable to locate a meaningful instruction to place after the load.

3. This kind of instruction requires memory access but doesn’t do anything, wasting a clock cycle.

4. Delayed load refers to the idea of postponing the use of data stored into memory.

Q15. What do you understand by locality of reference ?

Ans. According to the memory access pattern, a phenomenon known as locality of reference occurs when the same values or associated storage locations are often visited.

Q16. Write the difference between RAM & ROM.

Ans.

## Unit – 5 (Input/Output)

Q1. Why I/O devices cannot be connected directly to the system bus ?

Ans. VO devices cannot be connected directly to the system bus for the following reasons :

i. There are numerous peripherals that operate in a variety of ways. Therefore, integrating the necessary functionality to operate a variety of devices within the CPU would be impractical.

ii. The data formats and word lengths used by a computer system’s peripherals are typically different from those used by the system’s CPU.

Q2. What is function of VO interface?

Ans. Function of V0 interface are:

1. Data can be transferred between internal storage and external IO devices via input-output interface.

2. IO interfaces come with unique communication lines that allow peripherals to connect to the CPU. The differences between the CPU and peripheral, such as data transfer speed, mode of operation, etc., are overcome through these communication channels.

Q3. Compare memory and VO bus.

Ans.

Q4.  State the drawbacks of programmed I/O and interrupt driven I/O.

Ans. Drawbacks of programmed I/O and interrupt driven I/O:

i. The time that the CPU spends determining the status of I/O devices and carrying out various instructions for I/O data transfer is frequently better used for other tasks.

ii. The speed at which the CPU can test and maintain a device sets a cap on the I/O transfer rate.

Q5. Compare programmed I/O and interrupt driven I/O.

Ans.

Q6. Give comparison between I/O program controlled transfer and DMA transfer.

Ans.

Q7. State the characteristics of l/O channel.

Ans. i An I/O channel has a special-purpose processor.

ii. The I/O instructions are stored in main memory.

iii. The devices, region of memory storage, priority, and actions to be done for particular error circumstances are all specified by the l/O programme.

Q8. Explain the type of I/O channels.

Ans. There are two main types of I/O channels:

i. Selector channel

ii. Multiplexer channel

Q9. What are the modes of data transfer?

Ans. Modes of data transfer are:

i. Programmed I/O: I/O operations that are programmed are the outcome of I/O instructions that are written in computer programmes.

ii. Interrupt-driven I/O: This mode uses interrupt requests to get around the problems with programmed I/O.

iii. Direct memory access: The interface uses the memory bus to load and unload data from the memory unit.

Q10. What is an interrupt ?

Ans. 1. When the CPU is prepared to transfer or receive data from the memory, the I/O interface will signal the CPU with an interrupt.

2. When a CPU receives an interrupt signal, the current regular programme is stopped.

3. After stopping it saves the state of various registers in stack.

4. Following this, the CPU launches a subroutine to carry out the precise task specified by the interrupt.

Q11. Differentiate between synchronous and asynchronous transmission.

Ans.

Q12. Name the different types of I/O bus.

Ans. There are four types of I/O bus which are:

i Control command                                        ii. Output data command

iii. Status command                                       iv. Input data command

Q13. Why are read and write control lines in a DMA controller bidirectional ?

Ans. Read and write control lines in a DMA controller are bidirectional so that

1. The CPU can use the data bus to connect with the DMA registers to read from or write to the DMA registers when a BG input is set to 0.

2. When BG is 1, the CPU has given up control of the buses, allowing the DMA to connect to the memory directly by providing an address in the address bus and turning on RD or WR.

Q14. What is the use of modem in synchronous communication ?

Ans. A modem converts audio tones from the telephone line into digital signals for use by machines and digital signals into audio tones for transmission over telephone lines. The internal clocks of the modems used for synchronous transmission are set to the frequency at which bits are sent over the communication connection.

Q15. Describe cycle stealing in DMA.

Ans. 1. Cycle stealing is a technique used in Direct Memory Access (DMA) that enables I/O controllers to read or write RAM without interfering with the CPU.

2. DMA controllers have a cycle stealing mode of operation where they grab control of the bus for each byte of data being transmitted before handing it back to the CPU.

Q16. Write the difference between serial and parallel communication.

Ans.